Effect Of Channel Engineering Research Articles

Channel engineering for optimizing the electro‐thermal characteristics in p‐type GAA nanosheet transistors

AbstractIn this paper, we report simulation results for capacitance–voltage characteristics and temperature distribution in the cross‐section of p‐type gate‐all‐around nanosheet channel using an in‐house developed numerical simulator. The effects of material, channel width, and crystallographic orientation on electrical and thermal properties of p‐type nanosheet transistor are comprehensively investigated. The effect of channel engineering is analyzed, by evaluating density‐of‐states, hole density, current densities as well as distributions of temperature in the channel cross‐section. Finally, the thermal reliability of the device is addressed in terms of thermal resistance. The density‐of‐states and the hole density distribution at the oxide/channel interface can well explain the effective intrinsic capacitance obtained from the simulation. The better uniformity of the hole density distribution across the cross‐section of (110)/[001] channel, shows good promise for less performance fluctuation in terms of the thermal reliability issue.

Effect of Channel Engineering on Quasi-Static Capacitance-Voltage Characteristics of Double-Gate MOSFET

The quasi-static capacitance–voltage (QSCV) characteristics of 10-nm-gate-length double-gate N-type metal–oxide–semiconductor field-effect transistors (NMOSFETs) with Si, Ge, InAs, $$ {\hbox{In}}_{0.53} {\hbox{Ga}}_{0.47} {\hbox{As}} $$ , and GaAs as channel materials are studied and simulated using Silvaco ATLAS three-dimensional (3D) technology computer-aided design (TCAD) software. The QSCV approach offers the advantage of immunity against frequency dependence effects and the ability to measure small capacitances in the 100 fF range. In this device, we consider the self-consistent solution of Schrodinger’s equation with Poisson’s equation. The splitting of the conduction band into multiple subbands is considered, while there is no doping in the channel region. The effects of metal gate electrode engineering, channel engineering (Si, Ge, GaAs, $$ {\hbox{In}}_{0.53} {\hbox{Ga}}_{0.47} {\hbox{As}} $$ , and InAs), and different channel thicknesses with $$ \left( {{\hbox{Al}}_{2} {\hbox{O}}_{3} } \right) $$ as gate oxide having thickness of 0.8 nm on the QSCV characteristics are studied. A comparison of the QSCV characteristics is carried out for the above-mentioned channel materials, revealing a significant reduction in the inversion-mode QSCV characteristics for all the materials due to quantization that results in a decrease in the overall gate-to-channel capacitance and hence increases the threshold voltage of the MOS device. The QSCV characteristics are also useful to measure the oxide thickness, flat-band voltage, threshold voltage, maximum depletion region thickness, charge distribution in the dielectric, interface trap charge, and interface states between the channel and gate oxide before device fabrication.

THE IMPACT OF CHANNEL ENGINEERING ON SHORT CHANNEL BEHAVIOR OF NANO FIN-FETs

This short note presents the simulation result on the effect of channel engineering i.e., non-uniform channel doping on short channel effects (SCE) in nano Fin-FET devices using Silvaco TCAD tool. The nano Fin-FET structures were generated using DEVEDIT and the effect of channel doping concentration has been studied. The optimum doping concentration profile has been observed to considerably improve the SCE in general and drain induced barrier lowering (DIBL) in particular.